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Memory Chip on ... |
AX309 Xilinx Spartan-6 Development Board |
easyFPGA Spartan-6 Development Board |
|
Manufacturer |
Hynix |
Winbond |
|
Part |
H57V2562GTR-75C |
W9864G6JH-6 |
|
Type |
SDRAM |
SDRAM |
|
Value |
4M x 4Bank x 16 Bits |
1M x 4Banks x 16 Bits |
|
Clock |
133MHz |
166 MHz |
|
Pins |
54 |
54 |
|
Voltage |
3.3V |
3.3V |
|
Interface |
LVTTL |
LVTTL |
|
Access Time |
6ns |
6ns |
SDR SDRAM
This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate).
Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns). Clock rates up to 200 MHz were available.
**Note: The Papilio DUO includes a 512KB ISSI IS61WV5128 SRAM chip. SRAM is much, much easier to use with FPGA projects since there are no special timing (clock) requirements to follow. Static RAM (SRAM) has access times as low as 10 ns.
DDR SDRAM
The Spartan-6 also has an internal memory control block (MCB) which provides a DDRx controller to designs without consuming significant FPGA fabric.
|
|
DDR |
SDRAM |
|
Voltage |
2.5 Volts (standard); 1.8 V (low voltage) |
3.3 Volts |
|
Speed |
200 MHz, 266 MHz, 333 MHz, 400 MHz |
66 MHz, 100 MHz, 133 MHz |
***Note: There is no memory controller on the TQG144 package.
