دفتر فنی مهندسی آموزه های هزاره سوم

entity ad9914_dds_ctrl is

    port

    (        

        clk : in std_logic; -- SYNC_CLK - 1/24 REF_CLK

        rst : in std_logic;

        -- Parallel programming consists of 8 address lines and either

        -- 8 or 16 bidirectional data lines for R/W operations. The logic

        -- state on Pin 22 determines the width of the data lines used.

        DDS_PDIO : inout std_logic_vector(31 downto 0);        

        DDS_PSEL : out std_logic_vector(2 downto 0); -- Profile Select   

        -- The state of the external function pins (F0 to F3) determine

        -- the type of interface used by the AD9914

        DDS_FUNC : out std_logic_vector(3 downto 0);       

        DDS_OSHK : out std_logic; -- Output Shift Keying       

        -- The ramp direction (rising or falling) is externally controlled

        -- by the DRCTL pin. An additional pin (DRHOLD) allows the user

        -- to suspend the ramp generator in its present state.

        DDS_DRCTRL : out std_logic; -- Ramp Direction

        DDS_DRHOLD : out std_logic; -- Ramp Hold

        DDS_DROVER : in std_logic;  -- Ramp Over

        DDS_UPDATE : out std_logic; -- Update Internal Registers

        DDS_PWRDWN : out std_logic; -- External Power-Down

        DDS_MRESET : out std_logic; -- Master Reset

----------------------------------------------------------------------------------       

        dds_frq : in std_logic_vector(31 downto 0);   

        dds_phs : in std_logic_vector(15 downto 0);   

        dds_amp : in std_logic_vector(11 downto 0);

        dds_load : in std_logic;

        dds_mrst : in std_logic;

        dds_ramp : in std_logic_vector(1 downto 0);

        dds_duty : in std_logic_vector(3 downto 0); -- Function Description

        dds_dsrc : in std_logic_vector(2 downto 0); -- DDS Data Source

        dds_rsel : in std_logic_vector(2 downto 0)  -- Phase/Prequency Profile

    );

end ad9914_dds_ctrl