entity ad9914_dds_ctrl is
port
(
clk : in std_logic; -- SYNC_CLK - 1/24 REF_CLK
rst : in std_logic;
-- Parallel programming consists of 8 address lines and either
-- 8 or 16 bidirectional data lines for R/W operations. The logic
-- state on Pin 22 determines the width of the data lines used.
DDS_PDIO : inout std_logic_vector(31 downto 0);